Wafer level packaging processes can be broadly divided into two categories: Fan-In Wafer Level Packaging and Fan-Out Wafer Level Packaging processes. Fan-In Wafer Level Packaging processes enable the production of Fan-In Wafer Level Packages (FI-WLPs) containing one or more non-encapsulated die. Fan-In Wafer Level Packaging processes can be performed entirely on the wafer level, while producing FI-WLPs having planform dimensions equal to or nearly equal to the size of die (also commonly referred to as “Chip Scale Packages”). Electrical interconnection between the packaged die and the external contact array can be provided by a leadframe, an interposer, or a number of redistribution layers (RDLs), depending upon the particular packaging approach employed. By comparison, Fan-Out Wafer Level Packaging processes allow the production of larger Fan-Out Wafer Level Packages (FO-WLPs) having peripheral fan-out areas, which enlarge the surface area of the package topside over which a contact array can be formed. In an example of one known FO-WLP packaging approach, an array of singulated die is encapsulated in a molded panel over which one or more RDLs and a Ball Grid Array (BGA) are produced. The RDLs contain one or more metal levels or layers, which are patterned to define interconnect lines electrically coupling the packaged die to the BGA solder balls. After formation of the RDLs and the BGA, the panel is singulated to yield a number of microelectronic packages each containing a semiconductor die embedded within a molded body. Relative to CSP packages, FO-WLPs typically provide an increased I/O pin count and superior mechanical protection of the packaged die.
Prior to producing a BGA on a WLP, a solder mask layer is deposited over the outermost or last patterned metal level and lithographically patterned to create openings exposing selected regions of the interconnect lines within the metal level. Solder balls are deposited in the solder mask openings and contact the exposed regions of the interconnect lines. Solder reflow is then performed to bond the solder balls to interconnect lines. By common practice, the solder balls are deposited to sizes exceeding the planform dimensions of the solder mask openings such that, after reflow, the solder balls fill and cover the openings over which they are deposited. In general, this produces a structurally robust contact array. However, in rare instances, crack formation and delamination can occur within the RDLs at or near the interfaces between the solder mask layer and the BGA solder balls after prolonged thermal cycling. Crack formation within the RDLs can negatively impact WLP performance and can potentially result in rejection of the WLP due to failure during electrical testing.
There thus exists an ongoing need to provide WLPs and methods for fabricating WLPs that include solder balls deposited over one or more RDLs, while having a reduced likelihood of crack formation and delamination at or near the solder ball-RDL interfaces. Other desirable features and characteristics of the present invention will become apparent from the subsequent Detailed Description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Background.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.